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GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
Rev. 07 -- 3 February 2009 Product data sheet
1. General description
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus. The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling receiver or as a TTL-to-GTL interface. The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V CMOS outputs. The GTL2005 Vref linearity degrades below 0.8 V (see Section 10.1). If the application allows, use the GTL2014, otherwise more closely review noise margins.
fast tPD
GTL2005
GTL2014
slow tPD GTL- GTL GTL+
002aab378
Fig 1.
GTL2005/GTL2014 positioning
2. Features
I Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+ driver I Quad bidirectional bus interface I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O I Live insertion/extraction permitted I Latch-up protection exceeds 500 mA per JESD78 I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101 I Package offered: TSSOP14
NXP Semiconductors
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
3. Quick reference data
Table 1. Quick reference data VCC = 3.3 V 0.3 V Symbol Ci Cio Parameter input capacitance input/output capacitance Conditions control inputs; VI = 3.0 V or 0 V A port; VO = VTT or 0 V B port; VO = 3.0 V or 0 V GTL; Vref = 0.8 V tPLH tPHL tPLH tPHL
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
Min -
Typ[1] 2.3 3.4 6.0
Max 3.5 5.0 7.0
Unit pF pF pF
propagation delay, Bn to An see Figure 7 propagation delay, An to Bn see Figure 8
-
2.1 1.9 4.1 4.4
2.3 2.6 5.9 5.9
ns ns ns ns
4. Ordering information
Table 2. Ordering information Tamb = -40 C to +85 C Type number GTL2005PW Topside mark GTL2005 Package Name TSSOP14 Description plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT402-1
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5. Functional diagram
GTL2005
A0
B0
A1
B1
A2
B2
A3
B3
002aab151
VREF
DIR
Fig 2.
Logic diagram of GTL2005
6. Pinning information
6.1 Pinning
DIR A0 A1 VREF A2 A3 GND
1 2 3 4 5 6 7
002aab150
14 VCC 13 B0 12 B1
GTL2005PW
11 GND 10 B2 9 8 B3 GND
Fig 3.
Pin configuration for TSSOP14
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6.2 Pin description
Table 3. Symbol DIR A0 A1 A2 A3 B0 B1 B2 B3 VREF GND VCC Pin description Pin 1 2 3 5 6 13 12 10 9 4 7, 8, 11 14 GTL reference voltage ground (0 V) positive supply voltage data inputs/outputs (B side, TTL) Description direction control input data inputs/outputs (A side, GTL)
7. Functional description
Refer to Figure 2 "Logic diagram of GTL2005".
7.1 Function table
Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Input DIR H L Input/output B (TTL) inputs An = Bn A (GTL) Bn = An inputs
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8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO Parameter DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage VI < 0 V A port B port VO < 0 V output in OFF or HIGH state; A port output in OFF or HIGH state; B port IOL IOH Tstg
[1]
Conditions
Min -0.5 -0.5[2] -0.5[2] -0.5[2] -0.5[2] [3]
Max +4.6 -50 +7.0 +4.6 -50 +7.0 +4.6 128 80 -64 +150
Unit V mA V V mA V V mA mA mA C
current into any output in the LOW state current into any output in the HIGH state storage temperature range
B port A port B port
-60
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 9 "Recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
[2] [3]
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Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
9. Recommended operating conditions
Table 6. VCC VTT Operating conditions [1] Conditions GTL- GTL GTL+ Vref reference voltage overall GTL- GTL GTL+ VI VIH VIL IOH IOL Tamb
[1] [2] [3]
[2]
Symbol Parameter supply voltage termination voltage
Min 3.0 0.85 1.14 1.35 0.5 0.5 0.76 0.87 0 0
[3]
Typ 3.3 0.9 1.2 1.5
2 V 3 TT
Max 3.6 0.95 1.26 1.65 1.8 0.63 0.84 1.10 3.6 5.5 [3]
Unit V V V V V V V V V V V V V V mA mA mA C
0.6 0.8 1.0 VTT 3.3 -
input voltage HIGH-level input voltage LOW-level input voltage
A port except A port A port except A port A port except A port
2 -40
0.8 -12 40 12 +85
HIGH-level output current B port LOW-level output current ambient temperature A port B port operating in free-air
Unused inputs must be held HIGH or LOW to prevent them from floating. Vref is normally 23VTT, but based upon application and noise margin requirements can be set anywhere within this range and does not need to follow GTL-/GTL/GTL+ specification. Nominally 50 mV around Vref. See Figure 4, Figure 5, and Figure 6 for actual performance versus Vref, VCC, and temperature.
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10. Static characteristics
Table 7. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = -40 C to +85 C. Symbol VOH Parameter HIGH-level output voltage Conditions B port; VCC = 3.0 V to 3.6 V; IOH = -100 A B port; VCC = 3.0 V; IOH = -12 mA VOL LOW-level output voltage A port; VCC = 3.0 V; IOL = 40 mA B port; VCC = 3.0 V; IOL = 4 mA B port; VCC = 3.0 V; IOL = 8 mA B port; VCC = 3.0 V; IOL = 12 mA II input current control inputs; VCC = 3.6 V; VI = VCC or GND A port; VCC = 3.6 V; VI = VTT or GND B port; VCC = 0 V or 3.6 V; VI = 5.5 V B port; VCC = 3.6 V; VI = VCC B port; VCC = 3.6 V; VI = 0 V IOFF IEX output OFF current high contention over voltage leakage current supply current additional supply current per input input capacitance input/output capacitance A port; VCC = 0 V; VI or VO = 0 V to 4.5 V B port; VCC = 3.0 V; VO = 5.5 V
[2]
Min VCC - 0.2 2.0 -
Typ[1] 50
Max 0.4 0.4 0.55 0.8 1 1 10 1 -5 100 125
Unit V V V V V V A A A A A A A
[2]
[2] [2] [2] [2]
ICC ICC[3] Ci Cio
A or B port; VCC = 3.6 V; VI = VCC or GND; IO = 0 mA B port or control inputs; VCC = 3.6 V; VI = VCC - 0.6 V control inputs; VI = 3.0 V or 0 V A port; VO = VTT or 0 V B port; VO = 3.0 V or 0 V
-
2.3 3.4 6.0
3 500 3.5 5.0 7.0
mA A pF pF pF
[1] [2] [3]
All typical values are measured at VCC = 3.3 V and Tamb = 25 C. The input and output voltage ratings my be exceeded if the input and output current ratings are observed. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
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10.1 Performance curves
1200 VTH+ and VTH- (mV) 1000 VTH+
002aab152
1200 VTH+ and VTH- (mV) 1000 VTH+
002aab153
VTH- 800 Vref VTH- 800 Vref
600
600
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
a. VCC = 3.0 V
b. VCC = 3.3 V
002aab154
1200 VTH+ and VTH- (mV) 1000
VTH+ 800 Vref VTH-
600
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
c. VCC = 3.6 V Fig 4. GTL VTH+ and VTH- versus Vref; Tamb = -40 C
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GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
1200 VTH+ and VTH- (mV) 1000 VTH+ Vref 800
002aab155
1200 VTH+ and VTH- (mV) 1000 VTH+
002aab156
VTH- 800
Vref
VTH-
600
600
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
a. VCC = 3.0 V
b. VCC = 3.3 V
002aab157
1200 VTH+ and VTH- (mV) 1000 VTH+ Vref 800
VTH-
600
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
c. VCC = 3.6 V Fig 5. GTL VTH+ and VTH- versus Vref; Tamb = +25 C
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GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
1200 VTH+ and VTH- (mV) 1000
002aab158
1200 VTH+ and VTH- (mV) 1000 VTH+
002aab159
VTH+ 800
VTH- 800 VTH- Vref
600
Vref
600
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
a. VCC = 3.0 V
b. VCC = 3.3 V
002aab160
1200 VTH+ and VTH- (mV) 1000 VTH+
800 VTH- Vref 600
400 0.5
0.6
0.7
0.8
0.9
1.0 Vref (V)
c. VCC = 3.6 V Fig 6. GTL VTH+ and VTH- versus Vref; Tamb = +85 C
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Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
11. Dynamic characteristics
Table 8. Dynamic characteristics VCC = 3.3 V 0.3 V Symbol tPLH tPHL tPLH tPHL GTL; Vref = 0.8 V tPLH tPHL tPLH tPHL GTL+; Vref = 1.0 V tPLH tPHL tPLH tPHL
[1] All typical values are at VCC = 3.3 V and Tamb = 25 C.
Parameter propagation delay, Bn to An propagation delay, An to Bn
Conditions see Figure 7 see Figure 8
Min -
Typ[1] 2.1 1.9 4.1 4.4 2.1 1.9 4.1 4.4 2.1 1.9 4.2 3.8
Max 2.3 2.6 5.9 5.9 2.3 2.6 5.9 5.9 2.3 2.6 5.7 5.4
Unit ns ns ns ns ns ns ns ns ns ns ns ns
GTL-; Vref = 0.6 V
propagation delay, Bn to An propagation delay, An to Bn
see Figure 7 see Figure 8
-
propagation delay, Bn to An propagation delay, An to Bn
see Figure 7 see Figure 8
-
11.1 Waveforms
VM = 1.5 V at VCC 3.0 V; VM = VCC/2 at VCC 2.7 V for B ports and control pins; VM = Vref for A ports.
3.0 V input 1.5 V tPLH 3.0 V VM VM 0V
002aab140 002aab141
1.5 V 0V tPHL VOH Vref Vref VOL
tp output
VM = 1.5 V for B port and Vref for A port
B port to A port
a. Pulse duration Fig 7. Voltage waveforms
b. Propagation delay times
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GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
3.0 V input Vref tPLH output 1.5 V Vref 0V tPHL VOH 1.5 V VOL
002aab163
PRR 10 MHz; Zo = 50 ; tr 2.5 ns; tf 2.5 ns
Fig 8.
Propagation delay, An to Bn
12. Test information
VCC PULSE GENERATOR VI DUT
RT CL 50 pF RL 500
VO
002aab006
Fig 9.
Load circuitry for switching times
VTT VCC PULSE GENERATOR VI DUT
RT CL 30 pF 25
VO
002aab143
Fig 10. Load circuit for A (GTL) outputs
RL -- Load resistor CL -- Load capacitance; includes jig and probe capacitance RT -- Termination resistance; should be equal to Zo of pulse generators.
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13. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 11. Package outline SOT402-1 (TSSOP14)
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Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10
Table 9. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 10. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 12.
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Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 11. Acronym CDM CMOS DUT ESD GTL HBM I/O LVTTL MM TTL Abbreviations Description Charged-Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Gunning Transceiver Logic Human Body Model Input/Output Low Voltage Transistor-Transistor Logic Machine Model Transistor-Transistor Logic
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16. Revision history
Table 12. Revision history Release date 20090203 Data sheet status Product data sheet Change notice Supersedes GTL2005_6 Document ID GTL2005_7 Modifications:
* *
Figure 2 "Logic diagram of GTL2005" modified: symbol for AND gate replaced and its direction reversed updated soldering information Product data sheet Product data sheet Product data Product data Product data Product data 853-2171 23901 853-2171 22353 GTL2005_5 GTL2005_4 GTL2005_3 GTL2005_2 GTL2005_1 -
GTL2005_6 GTL2005_5 (9397 750 14285) GTL2005_4 (9397 750 13104) GTL2005_3 (9397 750 07222) GTL2005_2 (9397 750 06695) GTL2005_1 (9397 750 06497)
20070906 20050406 20040510 20000619 19990917 19990917
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17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 10.1 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Performance curves . . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering of SMD packages . . . . . . . . . . . . . . 14 Introduction to soldering . . . . . . . . . . . . . . . . . 14 Wave and reflow soldering . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 February 2009 Document identifier: GTL2005_7

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